A recent trend in direct-conversion receivers is to use subsampling. The basic approach is to sample the RF signal at an integer fraction of the carrier frequency greater than twice the bandwidth of the modulating signal. Spectral images of the modulating signals are repeated and down-conversion can be achieved by a low pass filter.
A general scheme based on subsampling operation is presented in D. H. Shen et al., “A 900-MHz RF front-end with integrated discrete-time filtering,” IEEE JSSC, Vol.31, pp. 1945-1954, December 1996 (hereinafter Shen), and is shown in FIG. 1. The RF input is sampled-and-held and followed directly by discrete time analog signal processing. The baseband signal is converted using an A/D converter. Sampling the carrier frequency fc at a rate fs results in spectral images located at nfs±fc where n is an integer. A desired spectral image can be filtered using a discrete time analog filter. In this approach, the lowest power solution would involve a tradeoff analysis between the input rate of the A/D converter and the complexity of anti-aliasing filters (see Shen) by appropriate selection of fs in relation with fc. In this approach, channel select filtering, demodulation and baseband processing are done in the digital domain following the A/D converter. The final stages of the multi-stage analog filters can also be used to reduce the adjacent channel interferers, thereby reducing the dynamic range requirement and power dissipation of the A/D converter.
E. Cijvat et al, “A 1.8 GHz subsampling CMOS downcoversion circuit for integrated radio applications,” ISCAS 1998, Vol. 3, pp. 149-152, discloses a subsampling mixer implemented for 1.8 GHz RF system. The mixer is implemented using a track-and-hold circuit. A differential OTA is used to transfer the sampled charge to the output in order to cancel the charge feed-through and to attain high linearity. The speed of OTA determines the maximum fs.
Another example of the subsampling approach is disclosed in A. Rofourgaran et al., “A single-chip 900-MHz spread-spectrum wireless transceiver in 1 um CMOS. II. Receiver design,” IEEE JSSC, Vol. 33, pp. 535-547, April 1998, for a short-distance wireless binary FSK transceiver at 900 MHz. This approach substantially reduces power dissipation by hard-limiting the filtered output of a subsampling mixer. The high frequency images are rejected by −60 dB using a switched capacitor analog filter. The limiter serves to act as a 1-bit A/D converter which provides an over-sampled down-converted baseband signal. The signal is decoded using a 1-bit FSK demodulator. The AGC functionality is achieved using the filter, limiter and demodulator. This structure is simpler than the general architecture that typically requires a multibit A/D converter and VGAs, and thereby saves power. However, its application is not directly extendable to general modulation schemes.
Conventional subsampling receiver designs eliminate the need for IF filters, image-reject mixers, image reject filters and analog I/Q branches, thereby permitting a high level of integration. Further, the LO (local oscillator) in such designs operates at a much lower frequency than fc. However, this design trades one set of problems for another. Exemplary disadvantages in such receivers typically include sensitivity to clock jitter and poor linearity.
Conventional receivers based on the subsampling principle require sample-and-hold (S/H) or track-and-hold stages operating at the IF rate. The signal-to-noise ration of such stages are limited by the clock jitter and settling time requirement of the S/H. Such stages cannot practically operate at RF frequencies because the required power dissipation will be prohibitively large for the required dynamic range performance (dictating quick settling time) and sampling frequency (dictating frequency aliasing).
It is therefore desirable to provide a subsampling receiver architecture that avoids problems such as those mentioned above with respect to the prior art.
A subsampling receiver architecture according to the invention can advantageously avoid problems such as mentioned above in the downconversion of a first periodic voltage waveform into a second periodic voltage waveform. A plurality of temporally distinct samples respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained, and the samples are combined to produce the second voltage waveform. The second waveform is driven by an amplifier stage. According to exemplary embodiments of the invention, the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.